Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of several SimRegress and SimCompare for improved simulation verification productivity.
SimRegress provides the ability to capture and replay the simulation testbench stimulus without having to run the full testbench thus supporting improved methods for 3rd party IP debug using tests directly from the customer SoC verification environment. Converters from the Avery database to Verdi FSDB and SimVision are supported to generate and inspect the waveforms.
SimCompare provides a smart diff feature between RTL and gate-level simulation. SimCompare correlates RTL and gate-level signal names and transaction synchronization between the two simulations being compared. The SimDiff application is integrated with Verdi and SimVision to directly scope these respective waveforms and source code debug tools and windows for more detailed inspection.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
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