Press release

Introducing SyntHESer, Aldec’s Proprietary High-Speed Synthesizer for HES Emulation and Prototyping

Sponsored by Businesswire

Aldec, Inc., a pioneer in mixed HDL language simulation and
hardware-assisted verification for FPGA and ASIC designs, has developed
a high-speed HDL synthesizer called SyntHESer as a part of the company’s
HES-DVM emulation tool. Accordingly, users of HES-DVM can be spared from
investing money in, and time integrating, a third-party synthesizer.

As for performance, in a recent in-house bench test SyntHESer performed
10x faster than a leading standalone synthesis tool when handling
identical blocks of HDL for a circa 45-million-gate Deep Learning
Accelerator (NVDLA) design. Multiple synthesis jobs can be run
concurrently on HES-DVM, and for the NVDLA design SyntHESer took less
than 20 minutes to synthesize the HDL.

“We’re delighted to unveil SyntHESer at this year’s DAC, which is in our
home state,” says Zibi Zalewski, General Manager of Aldec’s Hardware
Division. “It’s also our 35th Anniversary and it’s very much
part of Aldec’s DNA to develop and bring to market essential and core
EDA functionality. For example, a year after Aldec established in 1984,
we introduced our first official product. It was an MS-DOS-based
gate-level simulator called the Standard Universal Simulator for
Improved Engineering (SUSIE), and was the foundation for what today is
our Active-HDL™ product. Now in our fourth decade it’s great to still be
introducing solutions that improve the productivity of engineers.”

Languages supported by SyntHESer are VHDL, Verilog and SystemVerilog.

SyntHESer debuts as an integral part of HES-DVM, Aldec’s fully automated
and scalable hybrid verification environment for SoC and ASIC designs,
allowing for much faster design setups for emulation and prototyping

Aldec’s HES-DVM and SyntHESer will be on show at DAC 2019 on booth #623
at DAC 2019.

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design
Verification and offers a patented technology suite including: RTL
Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC
Prototyping, Design Rule Checking, CDC Verification, IP Cores,
High-Performance Computing Platforms, Embedded Development Systems,
Requirements Lifecycle Management, DO-254 Functional Verification and
Military/Aerospace solutions.