OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure, and trusted integrated circuits, today announced several technical speaking engagements focused on the next generation verification challenges facing today’s SoC designers. The presentations and participation at various industry events will educate developers and designers on how to properly address the challenges associated with verifying today’s complex systems.
OneSpin will present at the following events kicking off February 25 through March 19, 2020:
Xilinx Technology Day
Rishon Lezion, Israel – February 25
Embedded World 2020
Nuremberg, Germany – February 25 – 27
OneSpin will co-exhibit at booth 4-560 in partnership with eVision Systems and will be represented in the RISC-V Foundation pod (3A-536) presenting the company’s RISC-V verification solutions.
Presentation: Verification of RISC-V SoC Designs Using Formal Methods
Tuesday, February 25, 3:00 PM – 3:30 PM
Verification of system-on-chip (SoC) designs containing RISC-V processor cores is challenging. The cores can come from many sources, so they must be vetted for compliance to the instruction set architecture (ISA) specification. Beyond the ISA, optional features, custom extensions, and microarchitectural implementation must also be verified. The SoC team must guarantee proper integration of the cores and the entire chip must be screened for design issues that could hinder proper operation. Further, both cores and SoC must be checked thoroughly to ensure that no hardware Trojans or security risks are present. Only formal methods can provide full proofs for all these verification tasks and build confidence in the integrity of the design. This paper describes a formal-based methodology to meet these challenges, summarizes previous work on multiple RISC-V cores and SoCs, and presents previously unpublished results.
DVCon 2020, United States
San Jose, CA – March 2 – 5
OneSpin will exhibit at booth 1104 showcasing the company’s formal verification solutions for advance process nodes.
Cape Canaveral, FL – March 9 – 10
Presentation: Hardware Assurance Activities to Enable Cyber Physical System Security
Monday, March 9, 9:30 – 11:45 AM
The DoD encourages the acquisition community to utilize industry standards where possible. Attendees will hear about the SAE G-32 Committee that brings together many industry sectors (aerospace, automotive, banking, industrial control systems, medical, etc.) to address identified gaps in Cyber Physical Systems Security Systems (CPSS). An early focus of the committee has been the need for verification and validation (V&V) tools and their ability to analyze and verify that microelectronic components and the embedded software function only as intended. Leveraging work from the SAE G-19A Tampered Subgroup that addresses counterfeit detection in the form of identifying undocumented/undesired functionality at the component level, this committee has started compiling a list of tools and techniques that identify defects in components and encourage designed-in security. These methods that detect counterfeit and malicious function can be extended to include verifying the absence of known vulnerabilities throughout the lifecycle.
San Diego, CA – March 16 – 19
OneSpin will exhibit at booth 610 showcasing its IC integrity verification solutions for functionally correct, safe, trusted and secure designs.
Presentation: Integrated Circuit Authentication
34.3 An Automated Pre-Silicon IP Trustworthiness Assessment for Hardware Assurance
Thursday, March 19, 8:20 -10:30 AM
Integrated circuits designs include in-house and third-party intellectual properties that could contain hardware Trojans. An independent, trusted, and complete IP model, suitable for automated formal comparison with the IP register-transfer level (RTL) code using commercially available tools, may be used to prove absence of Trojans. Such models are generally not available, except for certain critical IPs, for example RISC-V processor cores. The development of these models may be costly and time consuming. This paper proposes an IP trustworthiness assessment process that does not require a trusted model. The approach uses automated tools that scan the IP RTL code to detect suspicious or unusual code patterns and known Trojan signatures. This low effort, objective assessment may detect Trojans and provide warnings that, depending on the specific project circumstances, may require additional investigation. The approach is demonstrated on numerous open-source and proprietary test designs containing hardware Trojans.
FPGA Security – Accellera: IP Security Assurance Standard
Tuesday, March 17, 3:30-5:10 PM
Participant: Accellera Systems Initiative IP Security Assurance Workgroup
About OneSpin Solutions
OneSpin Solutions is a leading provider of certified IC integrity verification solutions for building functionally correct, safe, secure, and trusted integrated circuits. These solutions are based on OneSpin’s widely used formal verification technology and assure the integrity of SoCs, ASICs and FPGAs. Headquartered in Munich, Germany, OneSpin partners with leaders worldwide in automotive and industrial applications; defense; avionics; artificial intelligence and machine learning; consumer electronics; and communications. Its advanced solutions are well-suited for developing heterogeneous computing platforms, using programmable logic, and designing and integrating processor cores, such as RISC-V. OneSpin’s customer-oriented commitment is fundamental to its growth and success. OneSpin: Assuring IC Integrity. Visit www.OneSpin.com to learn more.
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