Press release

Riviera-PRO™ Users to Benefit from Automatic UVM Register Generation Plus the Latest Verification Methodology Libraries

Sponsored by Businesswire

, a pioneer in mixed HDL language simulation and
hardware-assisted verification for FPGA and ASIC designs, has introduced
automatic UVM register generation to Riviera-PRO™, the company’s
advanced verification platform. Accepting a CSV file or IP-XACT register
description as an input, Riviera-PRO™ will, working at the Register
Abstraction Layer (RAL) of UVM, output files as RTL register models, C
headers and HTML.

In addition, libraries containing pre-compiled source code compliant
with the latest versions of UVM (IEEE 1800.2-2107) and UVVM
(2018.12.03), plus documentation and examples, have been added to
Riviera-PRO™ to facilitate easier and better test bench creation.

“Both enhancements to Riviera-PRO are of great benefit to users,”
comments Sunil Sahoo, Senior Corporate Applications Engineer. “Where the
automatic generation of UVM register models is concerned, it provides
major time-savings – certainly when the alternative is to hand-craft
hundreds or thousands of register models. As for verification
methodologies, we are dedicated to the provision of the most up-to-date

Other new features in Riviera-PRO™, release version 2019.04, include:

  • SystemVerilog users can create nets of integral data types (typedef);
  • The SystemVerilog compiler can work with sources for which the
    filename (including path name) is longer than 259 characters;
  • VHDL packages can be translated to SystemVerilog;
  • Support for Microsoft Visual Studio 2017 has been added; and
  • Debugging (Toggle Coverage analysis for VHDL) has been enhanced to
    include logic level transitions to and from high resistance (Z).

About Riviera-PRO™

Riviera-PRO™ addresses verification needs of engineers crafting
tomorrow’s cutting-edge FPGA and SoC devices. The tool enables the
ultimate testbench productivity, reusability, and automation by
combining the high-performance simulation engine, advanced debugging
capabilities at different levels of abstraction, and support for the
latest Language and Verification Library Standards.

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design
Verification and offers a patented technology suite including: RTL
Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC
Prototyping, Design Rule Checking, CDC Verification, IP Cores,
High-Performance Computing Platforms, Embedded Development Systems,
Requirements Lifecycle Management, DO-254 Functional Verification and
Military/Aerospace solutions.

Aldec is a registered trademark of Aldec, Inc. All other trademarks or
registered trademarks are the property of their respective owners.