SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced a comprehensive update to SiFive’s RISC-V Core IP portfolio with the public availability of the SiFive 20G1 release. The SiFive Core IP portfolio is a broad range of microarchitectures that scale from high-performance application processors, for running Linux-based applications or real-time deterministic workloads, to low-power microcontrollers focused on efficiency. SiFive Core IP is developed in partnership with customer requirements that include pre-integrated SiFive Insight, for advanced trace and debug capabilities, and SiFive Shield, for whole-SoC security.
“This release combines our roadmap enhancements with feedback from industry-leading customers to extend our leadership in RISC-V processor IP,” said Dr. Yunsup Lee, co-inventor of RISC-V and CTO of SiFive. “Our intent is always to deliver the best customer experience combined with a winning product portfolio, and the 20G1 release upholds that promise.”
SiFive RISC-V processor cores enable the creation of domain-specific heterogeneous SoCs, based on SiFive U-Series, S-Series, and E-Series Core IP. SiFive U-Series 64-bit processors are Linux-capable and multi-core ready, enabling high-performance core complexes for use in storage, networking, and AI inference processing applications. In this release, the SiFive U7-Series has increased load bandwidth up to 2.8x for memory-intensive workloads such as AI inference processing1. The SiFive 20G1 release also delivers lower power in the entire portfolio, with the SiFive U74 standard core running at up to 25% lower power2.
SiFive S-Series 64-bit processors and E-Series 32-bit processors are designed for real-time embedded applications, area-optimized for low power. Combining SiFive’s RISC-V processor cores to create heterogeneous multi-core complexes using domain-specific architectures for AI, aerospace, automotive, IoT, mobile, networking, storage, or vision applications. SiFive E-Series processors are now available with the RISC-V Embedded extension, RV32E, to deliver significant area saving with the SiFive E3-Series measuring up to 11% smaller area than previous versions.
SiFive Core IP seamlessly integrates into mixed-ISA designs with native Arm® CoreSight™ compatibility, enabling developers to leverage their existing software development environment. The suite of SiFive Freedom Tools has been updated to support the SiFive 20G1 release, offering a comprehensive suite of SDKs, compilers, libraries, and code examples to accelerate adoption and use of SiFive RISC-V processor Core IP.
“SiFive’s leadership and talent in RISC-V are demonstrated in the quality and breadth of our products,” said Dr. Naveed Sherwani, Chairman, President & CEO of SiFive. “SiFive’s customers return because of our winning product portfolio and our great CX team to help develop new products quickly and efficiently.”
The SiFive 20G1 release is now available through the award-winning SiFive Core Designer to simplify the selection and configuration of RISC-V cores for domain-specific architecture designs. The full details of the SiFive 20G1 release are available in our launch blog here.
SiFive is on a mission to free semiconductor roadmaps and declare silicon independence from the constraints of legacy ISAs and fragmented solutions. As the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all markets to build customized RISC-V based semiconductors. Founded by the inventors of RISC-V, SiFive has 16 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, please visit www.sifive.com.
1 – 2.8x higher performance based on SiFive internal engineering measurement of improving performance in memory-intensive workloads running on a SiFive U7-Series processor core
2 – 25% lower power based on SiFive internal engineering measurement of SiFive U74 processor (20G1) core power consumed while running Dhrystone benchmark as compared to SiFive U74 processor (19.08)
3 – 11% area reduction based on SiFive internal engineering measurement of SiFive E3-Series area using RISC-V Embedded extension RV32E in 28nm process technology vs. RV32I.
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