Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that
Socionext used the Cadence® full-flow digital and signoff
tools for the successful production tapeout of its latest large, 16nm
ASIC chip and has built a design environment for its 7nm designs. Using
the capabilities of the integrated full flow, Socionext sped design
closure on its 16nm design when compared with its previous solution.
The Socionext certified flow for the 16nm and 7nm designs includes the
Cadence Genus™ Synthesis Solution, Cadence Conformal®
Equivalence Checker, Cadence Innovus™ Implementation System,
Cadence Quantus™ Extraction Solution, Cadence Tempus™
Timing Signoff Solution, Cadence Voltus™ IC Power Integrity
Solution, and Cadence Physical Verification System (PVS). For more
information on the Cadence full-flow digital and signoff tools, please
In particular, the Tempus Timing Signoff Solution enabled the Socionext
team to meet design productivity goals for its 16nm production designs
by using the Tempus SmartScope hierarchical models. The Tempus
SmartScope models facilitate hierarchical static timing analysis (STA)
signoff and signoff-accurate engineering change orders (ECOs) by letting
users dynamically abstract portions of the design so they can analyze
blocks with accurate chip-level context. Additionally, the Voltus IC
Power Integrity Solution enabled Socionext to reduce electromigration
(EM) analysis turnaround time by 60 percent, which is critical for 16nm
and below FinFET process technologies.
For Socionext’s 7nm design, the Innovus Implementation System’s Flex
H-Tree capability in particular has already proven to be critical in
enabling power, performance and area (PPA) benefits. The Flex H-Tree is
an advanced clock synthesis technology that enables users to consider
floorplan blockages and power tradeoffs, allowing Socionext to meet its
target goal for clock skews.
“As a leading ASIC and ASSP product supplier for various market
segments, power, performance and area as well as overall turnaround time
are incredibly important to us,” said Mr. Takuya Yasui, General Manager
of LSI Development Division, Automotive & Industrial Business Group at
Socionext Inc. “We have successfully used the Cadence full-flow digital
and signoff tools to deliver multiple chips at 16nm and have chosen the
Cadence flow as our plan of record for both our 16nm and 7nm designs.
Our close collaboration with Cadence was essential for our 16nm design
success, and the Cadence full flow is now also an integral part of our
development of future 7nm products.”
“We recognize that the ASIC and ASSP market presents growing competitive
requirements and design challenges, including added design complexity
and shorter time-to-market demands,” said Dr. Chin-Chi Teng, senior vice
president and general manager of the Digital & Signoff Group at Cadence.
“Cadence has collaborated with Socionext to successfully deploy the
Cadence full-flow digital and signoff tools to help achieve design
success. We look forward to continuing to support them with future
From synthesis through implementation and signoff, the Cadence
integrated full-flow digital and signoff tools provide a fast path to
design closure and better predictability. The digital and signoff full
flow supports the company’s overall Intelligent System Design strategy,
which enables system and semiconductor companies to create complete,
differentiated end products more efficiently.
Cadence enables electronic systems and semiconductor companies to create
the innovative end products that are transforming the way people live,
work and play. Cadence software, hardware and semiconductor IP are used
by customers to deliver products to market faster. The company’s
Intelligent System Design strategy helps customers develop
differentiated products—from chips to boards to systems—in mobile,
consumer, cloud data center, automotive, aerospace, IoT, industrial and
other market segments. Cadence is listed as one of Fortune Magazine’s
100 Best Companies to Work For. Learn more at cadence.com.
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